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1 of 22 072401 features real-time clock keeps track of hundredths of seconds, minutes, hours, days, date of the month, months, and years 512k x 8 nv sram directly replaces volatile static ram or eeprom embedded lithium energy cell maintains calendar operation and retains ram data watch function is transparent to ram operation month and year determine the number of days in each month; valid up to 2100 over 10 years of data retention in the absence of power full 10% operating range lithium energy source is electrically disconnected to retain freshness until power is applied for the first time dip module only ? standard 32?pin jedec pinout ? upward comparable with the ds1248 powercap ? module board only ? surface mountable package for direct connection to powercap containing battery and crystal ? replaceable battery (powercap) ? pin for pin compatible with other densities of ds124xp phantom clocks pin assignment ds1251/ds1251p 4096k nv sram with phantom clock www.maxim-ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 32-pin encapsulated package 740-mil flush a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a 15 a 17 we a 13 a 8 a 9 a 11 oe a 10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 a18/rst dq2 gnd 15 16 18 17 dq4 dq3 1 rst 2 3 a15 a16 nc v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a 17 a 14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 a 18 x1 gnd v bat x2 34-pin powercap module board (uses ds9034pcx powercap)
ds1251/ds1251p 2 of 22 ordering information ds1251yp?xxxy (5v) -ind industrial -70 70 ns access -100 100 ns access blank 32-pin dip module p 34-pin powercap module board* ds1251wp-xxxy (3.3v) -ind industrial -120 120 ns access -150 150 ns access blank 32-pin dip module p 34-pin powercap module board* *ds9034pcx (powerca p) required: (must be ordered separately) pin description a 0 ?a 18 ? address inputs ce ? chip enable oe ? output enable we ? write enable v cc ? power supply input gnd ? ground dq 0 ?dq 7 ? data in/data out nc ? no connection x1,x2 ? crystal connection v bat ? battery connection rst ? reset description the ds1251 4096k nv sram with phantom clock is a fully static nonvolatile ram (organized as 512k words by 8 bits) with a built?in real-time cloc k. the ds1251y has a self?contained lithium energy source and control circuitry wh ich constantly monitors v cc for an out?of?tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent garbled data in both the memory and real-time clock. the phantom clock provides timekeeping informa tion including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with less than 31 days, includi ng correction for leap years. the phantom clock operates in either 24?hour or 12?hour fo rmat with an am/pm indicator.
ds1251/ds1251p 3 of 22 ram read mode the ds1251 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) is active (low). the unique address specified by the 19 address inputs (a0?a18) defines which of the 512k bytes of data is to be accessed. valid data will be av ailable to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times and states are also satisfied. if oe and ce access times are not satisfi ed, then data access must be measured from the later occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. packages the ds1251 is available in two packages (32?pin dip and 34?pin powercap module). the 32?pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 34?pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the ds1251p after the completion of the surface mount process. mounting the powercap after the surface mount process prevents damage to the crystal and batte ry due to the high temperatures required for solder reflow. the powercap is keyed to prevent re verse insertion. the powercap module board and powercap are ordered separately a nd shipped in separate containers. the part number for the powercap is ds9034pcx. ram read mode the ds1251 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) is active (low). the unique address specified by the 19 address inputs (a0?a18) defines which of the 512k bytes of data is to be accessed. valid data will be av ailable to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times and states are also satisfied. if oe and ce access times are not satisfi ed, then data access must be measured from the later occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. ram write mode the ds1251 is in the write mode whenever the we and ce signals are in the active (low) state after address inputs are stable. the latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. ho wever, if the output bus has been enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge.
ds1251/ds1251p 4 of 22 data retention mode the 5 volt device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the power fail point, v pf , (point at which write protection occurs) the internal clock registers and sram are blocked from any access. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc pin to the backup battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3-volt device is fully accessible and data can be written or read only when v cc is greater than v pf . when v cc falls below the power fail point, v pf , access to the device is inhibited. if v pf is less than v bat , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v bat . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. all control, data, and address signals must be powered down when v cc is powered down. phantom clock operation communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits which must be matched by executing 64 consecu tive write cycles containing the proper data on dq0. all accesses which occur prior to recogniti on of the 64?bit pattern are directed to memory. after recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited. data transfer to and from the timek eeping function is accomplished with a serial bit stream under control of chip enable ( ce ), output enable ( oe ), and write enable ( we ). initially, a read cycle to any memory location using the ce and oe control of the phantom clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64?bit comparison register. next, 64 consecutive write cycles are executed using the ce and we control of the smartwatch. these 64 write cycles are used only to gain access to the phantom clock. ther efore, any address to the memory in the socket is acceptable. however, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requirement is to set aside just one address location in ram as a phantom clock scratch pad. when the first write cycle is executed, it is compared to bit 0 of the 64?bit comparison register. if a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored. if a read cycle occurs at any time during pattern recognition, the present sequence is abor ted and the comparison register pointer is reset. pattern recognition continues for a to tal of 64 write cycles as describe d above until all the bits in the comparison register have been matched (this bit pattern is shown in figure 1). with a correct match for 64?bits, the phantom clock is enabled and data transfer to or from th e timekeeping registers can proceed. the next 64 cycles will cause the phantom clock to either receive or transmit data on dq0, depending on the level of the oe pin or the we pin. cycles to other locations outside the memory block can be interleaved with ce cycles without interrupting the pattern recognition sequence or data transfer sequence to the phantom clock.
ds1251/ds1251p 5 of 22 phantom clock register information the phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64?bit pattern reco gnition sequence has been completed. when updating the phantom clock registers, each register must be handled in groups of 8 bits. writing and reading individual bits within a register could produce erroneous results. these read/write registers are defined in figure 2. data contained in the phantom clock register is in binary coded decimal format (bcd). reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. phantom clock register definition figure 1 note: the pattern recognition in hex is c5, 3a, a3, 5c, c5, 3a, a3, 5c. the odds of this pattern being accidentally duplicated and causing inadvertent en try to the phantom clock is less than 1 in 10 19 . this pattern is sent to the phantom clock lsb to msb.
ds1251/ds1251p 6 of 22 phantom clock register definition figure 2 am?pm/12/24 mode bit 7 of the hours register is defined as the 12? or 24?hour mode select bit. when high, the 12?hour mode is selected. in the 12?hour mode, bit 5 is th e am/pm bit with logic high being pm. in the 24?hour mode, bit 5 is the second 10?hour bit (20?23 hours). oscillator and reset bits bits 4 and 5 of the day register are used to control the reset and oscillator functions. bit 4 controls the reset (pin 1). when the reset bit is set to logic 1, the reset input pin is ignored. when the reset bit is set to logic 0, a low input on the reset pin will cause the phantom clock to abort data transfer without changing data in the watch registers. bit 5 controls the oscillator. when set to logic 1, the oscillator is off. when set to logic 0, the oscillator turns on and the watch becomes operational. these bits are shipped from the factory set to a logic 1. zero bits registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. when writing these locations, either a logic 1 or 0 is acceptable.
ds1251/ds1251p 7 of 22 battery longevity the ds1251 has a lithium power source that is designed to provide energy for clock activity, and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1251 continuously for the lif e of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at 25 c with the internal clock oscillator running in the absence of v cc power. each ds1251 is shipped from da llas semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the ds1251 will be much longer than 10 years since no lithium battery energy is consumed when v cc is present. clock accuracy (dip module) the ds1251 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. the clock is calibrated at the factory by dalla s semiconductor using special calib ration nonvolatile tuning elements. the ds1251 does not require additiona l calibration and temperature devi ations will have a negligible effect in most applications. for this reason, met hods of field clock calibration are not available and not necessary. clock accuracy (powercap module) the ds1251p and ds9034pcx are each individually test ed for accuracy. once mounted together, the module is guaranteed to keep time accuracy to within 1.53 minutes per month (35 ppm) at 25 c.
ds1251/ds1251p 8 of 22 absolute maximum ratings* voltage on any pin relativ e to ground -0.3v to +6.0v soldering temperature 260c for 10 seconds (dip) see note 13 see ipc/jedec standard j-std-020a for surface mount devices * this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. operating range range temperature v cc commercial 0 c to +70 c 3.3v 10% or 5v 10% industrial -40 c to +85 c 3.3v 10% or 5v 10% recommended dc operating conditions over the operating range parameter symbol min typ max units notes v ih 2.2 v cc +0.3v v 11 logic 1 voltage all inputs v cc = 5v 10% v cc = 3.3v 10% v ih 2.0 v cc +0.3v v 11 v il -0.3 0.8 v 11 logic 0 voltage all inputs v cc = 5v 10% v cc = 3.3v 10% v il -0.3 0.6 v 11
ds1251/ds1251p 9 of 22 dc electrical characteristics over the operating range (5v) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a 12 i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 510ma standby current ce = v cc ? 0.5v i ccs2 3.0 5.0 ma operating current t cyc = 70 ns i cc01 85 ma write protection voltage v pf 4.25 4.37 4.50 v 11 battery switch over voltage v so v bat v11 dc electrical characteristics over the operating range (3.3v) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a 12 i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 57ma standby current ce = v cc ? 0.5v i ccs2 2.0 3.0 ma operating current t cyc = 70 ns i cc01 50 ma write protection voltage v pf 2.80 2.97 v 11 battery switch over voltage v so v bat or v pf v11 capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 510pf input/output capacitance c i/o 510pf
ds1251/ds1251p 10 of 22 memory ac electrical characteristics over the operating range (5v) ds1251y-70 ds1251y-100 parameter symbol min max min max units notes read cycle time t rc 70 100 ns access time t acc 70 100 ns oe to output valid t oe 35 55 ns ce to output valid t co 70 100 ns oe or ce to output active t coe 55 ns5 output high z from deselection t od 25 35 ns 5 output hold from address change t oh 55 ns write cycle time t wc 70 100 ns write pulse width t wp 50 70 ns 3 address setup time t aw 00 ns write recovery time t wr 00 ns output high z from we t odw 25 35 ns 5 output active from we t oew 55 ns5 data setup time t ds 30 40 ns 4 data hold time from we t dh 55 ns4
ds1251/ds1251p 11 of 22 phantom clock ac electrical characteristics over the operating range (5v) parameter symbol min typ max units notes read cycle time t rc 65 ns ce access time t co 55 ns oe access time t oe 55 ns ce to output low z t coe 5ns oe to output low z t oee 5ns ce to output high z t od 25 ns 5 oe to output high z t odo 25 ns 5 read recovery t rr 10 ns write cycle time t wc 65 ns write pulse width t wp 55 ns 3 write recovery t wr 10 ns 10 data setup time t ds 30 ns 4 data hold time t dh 0ns4 ce pulse width t cw 60 ns reset pulse width t rst 65 ns power-down/power-up timing over the operating range (3.3v) parameter symbol min typ max units notes ce at v ih before power-down t pd 0 s v cc slew from v pf(max) to v pf(min) ( ce at v pf ) t f 300 s v cc slew from v pf(min) to v so t fb 10 s v cc slew from v pf(max) to v pf(min) ( ce at v pf ) t r 0 s ce at v ih after power-up t rec 1.5 2.5 ms (t a = 25c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
ds1251/ds1251p 12 of 22 memory ac electrical characteristics over the operating range (3.3v) ds1251w-120 ds1251w-150 parameter symbol min max min max units notes read cycle time t rc 120 150 ns access time t acc 120 150 ns oe to output valid t oe 60 75 ns ce to output valid t co 120 150 ns oe or ce to output active t coe 55ns5 output high z from deselection t od 40 70 ns 5 output hold from address change t oh 55ns write cycle time t wc 120 150 ns write pulse width t wp 90 100 ns 3 address setup time t aw 00ns write recovery time t wr 20 20 ns 10 output high z from we t odw 40 70 ns 5 output active from we t oew 55ns5 data setup time t ds 50 60 ns 4 data hold time from we t dh 20 20 ns 4 phantom clock ac electrical characteristics over the operating range (3.3v) parameter symbol min typ max units notes read cycle time t rc 120 ns ce access time t co 100 ns oe access time t oe 100 ns ce to output low z t coe 5ns oe to output low z t oee 5ns ce to output high z t od 40 ns 5 oe to output high z t odo 40 ns 5 read recovery t rr 20 ns write cycle time t wc 120 ns write pulse width t wp 100 ns 3 write recovery t wr 20 ns 10 data setup time t ds 45 ns 4 data hold time t dh 0ns4 ce pulse width t cw 105 ns reset pulse width t rst 120 ns
ds1251/ds1251p 13 of 22 power-down/power-up timing over the operating range (3.3v) parameter symbol min typ max units notes ce at v ih before power-down t pd 0 s v cc slew from v pf(max) to v pf(min) ( ce at v ih ) t f 300 s v cc slew from v pf(max) to v pf(min) ( ce at v ih ) t r 0 s ce at v ih after power-up t rec 1.5 2.5 ms (t a = 25c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
ds1251/ds1251p 14 of 22 memory read cycle (note 1) memory write cycle 1 (notes 2, 6, and 7)
ds1251/ds1251p 15 of 22 memory write cycle 2 (notes 2 and 8) reset for phantom clock read cycle to phantom clock
ds1251/ds1251p 16 of 22 write cycle to phantom clock
ds1251/ds1251p 17 of 22
ds1251/ds1251p 18 of 22 ac test conditions output load: 50 pf + 1ttl gate input pulse levels: 0?3v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 50 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. the expected t dr is defined as cumulative time in the absence of v cc with the clock oscillator running. 10. t wr is a function of the latter occurring edge of we or ce . 11. voltage are referenced to ground. 12. rst (pin1) has an internal pull?up resistor. 13. real?time clock modules can be successfully processed through conventional wave?soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap: a. dallas semiconductor reco mmends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live ? bug?). b. hand soldering and touch?up: do not touch or a pply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder.
ds1251/ds1251p 19 of 22 ds1251 4096k nv sram with phantom clock kg 32-pin dim min max a in. mm 1.680 42.67 1.740 44.20 b in. mm 0.715 18.16 0.740 18.80 c in. mm 0.335 8.51 0.365 9.27 d in. mm 0.075 1.91 0.105 2.67 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.140 3.56 0.180 4.57 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.010 0.25 0.018 0.46 k in. mm 0.015 0.38 0.025 0.64
ds1251/ds1251p 20 of 22 ds1251p pkg inches dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c - - 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.025 0.027 0.030 note: dallas semiconductor reco mmends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live ? bug?). hand soldering and touch?up: do not t ouch or apply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
ds1251/ds1251p 21 of 22 ds1251p with ds9034pcx attached pkg inches dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 components and placement may vary from each device type
ds1251/ds1251p 22 of 22 recommended powercap module land pattern inches pkg dim min nom max a - 1.050 - b - 0.826 - c - 0.050 - d - 0.030 - e - 0.112 -

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